Single event transient of SOI FinFET with total ionizing dose irradiation

1. Introduction

When an energetic ion hits the sensitive area of semiconductor device, single event transient (SET) may occur. With device feature size scaled down, SET plays an important role on the analysis of the reliability for integrated circuits under radiation environment [1-3]. As device feature size goes down into sub-micro or nanometer regime, short channel effects (SCEs), like drain induced barrier lowering (DIBL), degradation of off current, have become a serious concern for the device performances [4-6]. Fin-type field-effect-transistor (FinFET) is one of the emerging non-planar and multi-gate devices. Because of its higher speed, higher density, higher scalability and lower power, FinFET has been paid much attention for one of the most promising candidates to replace current CMOS technologies [7]. The sensitive of FinFETs to total ionizing dose (TID) effect can be reduced by thin silicon fins [7-9]. Although silicon-on-insulator (SOI) technology is helpful for improving the tolerance of devices to SET, the sensitivity of SOI device to TID is also serious due to the existence of oxide insulator [7-9]. Therefore, electronics devices for space environments experience TID and SET simultaneously [10-13]. Some simulation and experimental results have indicated that the SET pulse width and the sensitive area decrease due to heavy-ion induced dose for the IBM 180nm process [10]. However, for a 130 nm SRAM and the SEU- and SET-induced soft errors in 40-nm bulk circuits, the experimental results have shown increases in the neutron SEU cross section caused by TID irradiation [10].

In this work, the effect of TID on the response of SET for SOI FinFET at 14 nm technology node is explored. The paper is organized as follows: Section 2 presents the simulation model of SOI FinFET at 14 nm technology node. The impact of TID on SET is simulated and analyzed in Section 3. Section 4 concludes the paper.

2. Device model for FinFET

Based on TCAD, a 3D model of SOI FinFET at 14 nm technology node is simulated, shown in Fig. 1. The simulation parameters of the device are from ITRS 2013, shown in Table 1. Somephysical models are included. For simulating the presence of interface traps at the silicon/oxide interface, the direct recombination model is used. Compared with the density gradient model, the Bohm quantum potential (BQP) model converges and calibrates to the Schrodinger-Poisson model well. Therefore, BQP is used to model the effect of quantum mechanical confinement [14]. For obtaining the velocity saturation effect, the high-field saturation mobility model is also recommended. Because of the thermal generation, the devices always have the leakage currents, which is simulated by the Shockley-Read-Hall (SRH) recombination model. Along with the remote Coulomb scattering mobility model, the remote phonon scattering mobility model is included to describe the mobility reduction observed in high k gate dielectric FET devices [14]. For MOSFET, the degradation of the electron or hole mobility occurs inside inversion layers. To capture the correct performances of MOSFET, an inversion layer model from Lombardi is used.

When the SOI device behaves like a bipolar transistor, the band gap narrowing model is recommended to accurately simulate the bipolar current gain. To accurately simulate the impact ionization effect, we use a non-Maxwellian based model from Concannon. The Fermi-Dirac statistics are also selected to obtain the certain properties of very highly-doped devices.

The model of single event transient simulation due to an energetic particle strike is used [14]. The supply voltage is set to 0.8 V. The simulation result is good agreement with the experimental data of n-type SOI FinFET [15], as shown in Fig. 2.

Fig. 1Structure of 14 nm FinFET device

Fig. 2I-V electrical character curve for model and experiment results [15]

3. SET response of FinFET after TID

The effect of TID on SET sensitivity of 14nm SOI FinFET is studied. The device is at “off” state for 10 keV X-ray irradiation. The results of pre- and after irradiation are shown in Fig. 3.

It is clear that as the captured positive oxide trap charges in the SiO2 increase, the threshold voltage decreases [16]. After irradiation, the supply voltage of the device being 0.8 V, the drain currents for different linear energy transfer (LET) are shown in Fig. 4.

Fig. 3IDS-VGS curves for pre-irradiation, 50 krad (SiO2), 100 krad (SiO2), 500 krad (SiO2) and 1Mrad (SiO2) irradiation

Fig. 4Drain current for different LET of after irradiation device

a) 50 krad (SiO2)

b) 1 Mrad (SiO2)

For quantifying the influence of TID irradiation on the SET response of FinFET, the collected charger and the bipolar amplification coefficient are defined as below [17]:

where, $Q_c$ is the collected charge, $I_D\left(t\right)$ is the simulated drain current of the device, $\beta$ is the bipolar amplification coefficient, $Q_d$ is the deposited charge that can be obtained considering the Gaussian distribution of the ion track and the 3D geometry of the silicon body [18], and $t$ is the simulation time.

The collected charge is shown in Fig. 5. The comparison results of SET responses for different LET of FinFET after 50 krad (SiO2) and 1 Mrad (SiO2) irradiation are shown in Fig. 6, respectively.

It can be concluded that as total dose level is increased, the drain current peaks of FinFETs under the same LET conditions are slight fluctuant [19]. Their current peaks nearly increase with increasing LET linearly. However, with total dose level increasing from 50 krad (SiO2) to 1 Mrad (SiO2), the devices get a trend of first decrease then increase in the drain collected charge [10]. The reason may be that due to TID irradiation, the threshold voltage of the device reduces, which leads to the driven current of the device increase. A larger driven current gets a good immunity to SET [16, 20], resulting in the collected charge decrease. Simultaneously, after TID irradiation, large numbers of the positive hole trap charges are captured by the gate oxide [16]. Therefore, the potential of the channel is increased, resulting in that the drain diffuse current is enhanced. This fact leads to the collected charge increase. Based on the above analysis, due to competing mechanisms associated with decreasing threshold voltage and increasing the drain diffuse current, the collected charge first decreases with total dose and then increases. When LET is less than 10 pC/μm, due to TID irradiation, the device gets a significant increase in the bipolar amplification effect. The bipolar amplification coefficient can be obtained by the ratio between the collected charge and the deposited charge [17]. As LET increases, the bipolar amplification coefficient decreases and in the trend of a slight impact by the irradiation.

Fig. 5Collected charge for different LET of after irradiation device

a) 50 krad (SiO2)

b) 1 Mrad (SiO2)

Fig. 6SET response of device after irradiation

a) Current peak

b) Collected charge

c) Bipolar amplification coefficient

4. Conclusions

TID irradiation may change the transistor leakage currents or threshold voltage and then impacts SET sensitivity of the devices. The effect of TID on SET response of SOI FinFET at 14 nm technology node is investigated with irradiations at different dose levels. The results show that as total dose increases, the drain current peak under the same conditions present a slight fluctuant, while the collected charge and the bipolar amplification coefficient first decrease and then increase. The potential mechanism is also discussed.