Fault logic circuit design of switching power supply based on soft reference circuit module

2.1. Principle analysis of fault logic circuit

(1) Fault comparator.

The circuit structure of the fault comparator is shown in Fig. 1, and its ports are described as follows:

1) FAULT: Fault signal input (from the system).

2) FDC_OUT: Fault comparator output (connected to VIN_FDC terminal of the fault logic circuit).

As shown in Fig. 1, the 5 V power supply terminal is divided by two resistors $R_1$ and $R_2$ to obtain a 3 V reference voltage. The FAULT terminal signal and the 3V reference voltage are input to a comparator [13] composed of $Q_2$ and $Q_3$ through an emitter follower respectively. When the input voltage at FAULT is higher than 3 V, $Q_4$ and $Q_3$ are turned on, $Q_1$ and $Q_2$ are turned off, and FDC_OUT outputs high; when the input voltage at FAULT is lower than 3 V, $Q_4$ and $Q_3$ are turned off, $Q_1$ and $Q_2$ are turned on, and FDC_OUT outputs low [14].

Fig. 1Fault comparator circuit diagram

(2) Fault logic circuit.

The relationship between the fault logic circuit and the soft reference circuit module is shown in Fig. 2, and the fault logic circuit is shown in Fig. 3.

Fig. 2Module relationship diagram of fault logic circuit and soft reference circuit

The ports are described as follows:

1) VIN_5 V: 5 V power supply terminal.

2) VIN_FDC: input port (fault comparator FDC_OUT port).

3) UVLO: input port (UVLO port for undervoltage lockout).

4) SOFTREF: the soft reference pin of the chip is externally connected with a 0.1 uF capacitor to the ground.

5) VOUT_LOGIC: output port (monostable pulse generator VIN_AULT port).

Fig. 3Fault logic circuit diagram

2.2. Principle analysis of fault-free logic circuit

During normal operation (no fault generated), the VIN_UVLO terminal is low [15]. When there is no fault signal in the system, it can be seen from the above analysis that the VIN_FAULT1 and VIN_FAULT2 terminals are at high level. At this point, $Q_{16}$ turns off, causing $Q_{14}$, $Q_{15}$, and $Q_{17}$ to all turn off. $Q_{31}$ and $Q_{34}$ are also turned off. $Q_{30}$ is turned on, the current mirror formed by $Q_{25}$ and $Q_{29}$ is also turned on, and the current bias circuit works. The SOFTREF terminal of the external capacitor is charged by the power supply voltage through the branch of $Q_{25}$ and $R_{33}$ until the voltage of the SOFTREF terminal is clamped at 5 V by the clamping circuit [16].

How the 4 V comparator works: When the VIN_FAULT1 terminal is high, $Q_{16}$ is powered down and the 4 V comparator does not work. $Q_{16}$ is on when the VIN_FAULT 1 terminal is low. If the SOFTREF terminal voltage is higher than 4 V at this time, $Q_{17}$ is turned off; if the SOFTREF terminal voltage is lower than 4 V at this time, $Q_{17}$ is turned on. The SOFTREF is charged by the branch where $Q_{16}$ and $Q_{17}$ are located, the voltage of SOFTREF increases, and the collector voltage of $Q_{16}$ also increases [17]. When the SOFTREF terminal voltage is charged to about 4 V, $Q_{16}$ enters the saturation region. $Q_{14}$ is turned on. $Q_{15}$ is turned on. The $Q_{17}$ base level is pulled low. $Q_{17}$ is turned off, and then the 4 V comparator does not work [18].

Working principle of the 0.2 V comparator: during normal operation, the voltage at the SOFTREF terminal is about 5 V. $Q_{20}$ is turned off, and the level at the VOUT_FAULT terminal is low; in case of a fault, the SOFTREF terminal discharges through the $R_{31}$, $Q_{21}$, and $R_{32}$ loops, and the voltage at the SOftREF terminal gradually decreases. When the voltage at the SOFTREF terminal drops to 0.2 V, $Q_{20}$ is turned on. The level at the VOUT_FAULT terminal changes from low to high, acting on the fault module circuit [19]. When $Q_{20}$ is off, the emitter potential $V$ of $Q_{20}$ is given by:

When the VIN_FAULT terminal level goes from low to high, the VIN_REF terminal level also goes from low to high. It can be seen from the above analysis that in the previous state of the circuit, the base level of $Q_5$ is high. The base level of $Q_{13}$ is high. The terminal level of VOUT_LOGIC is high, and the terminal levels of VOUT_REF1 and VOUT_REF2 are low. If the VIN_REF level changes from low to high, $Q_{10}$ is turned on. The base level of $Q_5$ goes from high to low. The base level of $Q_{13}$ goes from high to low. The level of VOUT_LOGIC goes from low to high, and the levels of VOUT_REF1 and VOUT_REF2 go from low to high [20].

In summary, during normal operation, the 5 V power supply charges the SOFTREF terminal, and the voltage of the SOFTREF terminal gradually increases from 0 to 5 V, and then remains unchanged; the system generates a fault signal, and the SOFFREF terminal begins to discharge, and recharges when it discharges to 0. 2 V. During the recharging process, when the voltage at the SOFTREF terminal does not reach 4 V, a fault signal is generated [21]. At this time, the voltage at the SOFTREF terminal will continue to charge until it is charged to 4 V and then discharged again until it is discharged to 0.2 V and then charged again until it reaches 5 V, after which it remains unchanged [22].

3.1. Controller overall structure simulation

For the overall architecture of the chip, the controller chip is composed of multiple circuit modules, as shown in Fig. 4.

Fig. 4Overall architecture of the chip

Based on the ASMC 4 μm/40 V Bipolar process, the circuit is simulated and verified by using the Cadence Spectre software platform. Process angles (TT/SS/FF), supply voltages (12 V/20 V), and temperatures (–55 ℃/25 ℃/125 ℃) are considered. Parameters of peripheral basic components are: $C_{sr}=$ 0.1 μF, $R_{\mathrm{m}\mathrm{i}\mathrm{n}}=$ 86.6 kΩ, $R_{ange}=$ 7.15 kΩ, $C_{VCO}=$ 1 nF, $R=$ 4.02 kΩ and $C=$ 200 pF.

The function of the converter depends on the control loop. In the nonlinear closed-loop feedback loop, the Boost converter has an inherent right-half plane zero. The LC produces a pole. The load of the output stage produces a pole and the error amplifier also introduces a pole. There are multiple poles and zeros in the system, and the phase margin of the multi-pole system cannot be guaranteed, which will cause system instability. Therefore, the frequency compensation is needed. An R, C compensation network is connected at the output end of the error amplifier to provide a zero point for the system so as to improve the influence of the output pole on the phase margin. It also ensures that the phase margin of a feedback loop is larger than 60 and improves the stability of the system.

3.2. Failure circuit module simulation

The main function of the fault circuit module is fault detection and fault protection. The module is mainly composed of a fault comparator (FDC) and a fault logic circuit. The function of the fault comparator (FDC) is relatively simple. It mainly compares the input voltage of the FAULT terminal with the 3 V reference voltage to obtain a voltage signal. This signal passes through circuits such as fault logic to control the output of the MOSFET starter. When the input voltage is above the 3 V reference, the output of the FDC is high. When the input voltage is below the 3 V reference, the output of the FDC is low. Fig. 5 is a functional diagram of a fault circuit module.

Fig. 5Function diagram of faulty circuit module

4.1. Soft reference circuit module design

The main functions of the soft reference block are soft start, restart delay, and precision voltage reference. Wherein, the restart delay function needs to be realized in combination with the fault circuit module. Since the circuit function of the soft-reference circuit module is relatively complex, it will be analyzed from the perspective of the soft-Ref pin function in conjunction with Fig. 6.

As shown in Fig. 6, the Soft-Ref pin performs three functions: Soft-Start, Restart-Delay, and Precision Reference (5 V). In undervoltage lockout (UVLO), all outputs are low and the external capacitor $C_{sr}$ on the Soft-Ref pin is discharged. When the supply voltage VCC exceeds the UVLO upper limit, the internal current source charges $C_{sr}$ until it is clamped at 5 V by the 5 V clamp circuit. The soft start time is roughly given by:

In the event of a fault, all outputs are driven low. The external capacitor $C_{sr}$ is discharged by a 20 μA current source. This is the restart delay period. When $C_{sr}$ reaches 0.2 V, the output is enabled and $C_{sr}$ is charged with a 0.5 mA current. If a fault occurs before the end of the charge cycle, the output is immediately driven low, but $C_{sr}$ charges to 4 V before the 20 μA restart delay current discharges $C_{sr}$. The restart delay time during continuous fault operation is:

Fig. 6Functional diagram of soft reference circuit module

The restart delay function can be removed by adding a 100 kΩ resistor between the Soft-Ref pin and the 5 V pin. In this case, however, the fault detection circuit will permanently shut down the converter in the event of a fault. The converter does not return to normal operation until the VCC is reapplied and the UVLO circuit resets the fault circuit, leaving the external 100 kΩ resistor open. When a 100 kΩ resistor is connected, the soft start time becomes:

The precision reference at the Soft-Ref pin is due to an internal 5 V clamp. A 15 Ω resistor is connected between the Soft-Ref pin and the clamp circuit to avoid the regulated voltage fluctuation caused by the external capacitor.

4.2. Clock frequency output control algorithm

A voltage is taken from the output voltage and fed back to the error amplifier (EA). This feedback signal is compared to a 5 V reference voltage and an error voltage is an output. The error voltage is used as a control voltage to control the oscillation frequency of a voltage-controlled oscillator (VCO), and then a square wave signal is an output through a control logic circuit and an output driving circuit to drive a switch tube to control the working state of a peripheral circuit and finally keep the output voltage stable.

In a ZVS circuit, the output voltage will decrease as the frequency increases. Therefore, in practical applications, the inverting input of the EA should be connected to the reference voltage, and the non-inverting input of the EA should be connected to the feedback voltage.

Control the internal operating frequency, which is controlled by the error amplifier output.

The VCO is externally connected with two resistors $R_{ange}$ and $R_{\mathrm{m}\mathrm{i}\mathrm{n}}$ and a capacitor $C_{VCO}$. $R_{\mathrm{m}\mathrm{i}\mathrm{n}}$ and $C_{VCO}$ determine the minimum frequency:

When the output of the error amplifier is less than or equal to one diode drop, the VCO operates at the minimum frequency. The VCO frequency is at its maximum when the error amplifier output rises one diode drop below 5 V:

The usable frequency range is the difference between the first two equations:

Because the nominal output swing of the error amplifier is approximately 3.6 V due to a full-scale change in the VCO frequency, the gain of the VCO block is as follows:

5.1. Circuit simulation parameters

For Simulink simulation with ModelSim module, when all configurations are completed, MATLAB can be added to edit and verify the program. It can also make preparations for joint simulation, set the port and clock frequency, simulation accuracy, communication serial port, and set simulation parameters through 53885 for communication. After setting, the module is connected to the Buck circuit topology in Simulink to complete the drawing of Simulink simulation.

The parameter indexes mainly involved in the fault circuit module are shown in Table 1.

Simulation results of main parameters of the fault circuit module are shown in Table 2 and Table 3 respectively.

5.2. Comparison of simulation results for zero-crossing detection

The simulation results of the zero-crossing detection comparison and main parameters of the monostable pulse generator module are shown in Tables 4-6 respectively.

5.3. Results of the control logic circuit simulation

Fig. 7 is the function simulation waveform diagram of the control logic circuit module.

The parameters mainly involved in the control logic circuit module are shown in Table 7.

Simulation results of main parameters of the control logic circuit module are shown in Table 8.

Fig. 7Function simulation waveform of the control logic circuit module