Analysis and design of a novel hybrid topology for power quality improvement using multilevel inverter fed induction motor by reducing vibration for textile wastewater treatment applications

2.1. Buck-boost Cuk DC-link configuration

Buck Boost (BB) converter unit is associated with topsy-turvy DC sources. The identical structure of BDCLMLI is appeared in Fig. 4.

Number of levels in BBDCLCMLIFIM arrangement is determined as:

Number of switches in BDCLCMLI is given by (2):

where $R_{level}$ is the quantity of levels, $R_{Switch}$ is the quantity of switches in BBDCLCMLIFIM, Q-number of H-bridge inverter, S-number of DC sources and P-number of buck-help units.

2.2. Modes of operation

Mode 1: Output voltage = ±$V_{IN1}$ state.

Capacitor $C_1$ is charged to the information voltage $V_{IN1}$ through $D_{1b}$ by turning ON transistor $S_{1c}$. Transistors $S_{1a}$, $S_{1b}$ and diode $D_{1a}$ stay turned off. The DC voltage at this state is equivalent to $V_{IN1}$ as $V_{IN0}$ is closed by turning off transistor $S_{1a}$. Voltage source $V_{IN1}$ alone supplies capacity to the heap. Fig. 5(a) delineates the identical circuit for V0 = +$V_{IN1}$.

Mode 2: Output voltage = ±$V_{IN0}$ state.

For typical activity of the proposed inverter, $V_{IN0}>V_{IN1}$. In the DC-DC converter, just transistor $S_{1a}$ is turned ON while different transistors are turned off. Consequently, $V_{IN0}$ is associated with the DC bus through diode $D_{1a}$. As $V_{IN0}>V_{IN1}$, diode $D_{1b}$ is turn around one-sided and henceforth squares $V_{IN1}$. Fig. 5(b) delineates the proportionate circuit for $V_0=+V_{IN0}$. The capacitor $C_1$ is open at this state. Along these lines, its voltage stays at $V_{IN1}$.

Fig. 5Operating modes of proposed BBDCLCMLIFIM

a) IM-Induction motor

b)

c)

d)

Mode 3: Output voltage = ±($V_{IN0}+V_{IN1}$) state.

Capacitor $C_1$ charged to $V_{IN1}$, is associated in arrangement with info voltage source $V_{IN0}$ by turning ON transistors $S_{1a}$ and $S_{1b}$. Diode $D_{1b}$ is turn around one-sided and blocks $V_{IN1}$. The net voltage that shows up over the DC transport currently is equivalent to $V_{IN0}+V_{IN1}$. In this state, input voltage source $V_{IN0}$ and capacitor $C_1$ supply capacity to the heap. Fig. 5(c) delineates the proportionate circuit for $V_0=+(V_{IN0}+V_{IN1})$.

Mode 4: Output voltage = 0 V state.

To acquire zero dimension at the output after the positive half cycle Fig. 5(d), just transistor $Q_1$ is turned ON, while the various switches in the H-bridge inverter stay killed. The diode of transistor $Q_2$ is utilized for nothing wheeling. Essentially, to get zero dimension at the output after the negative half cycle, just transistor $Q_4$ is turned ON, while the various switches in the full scaffold inverter stay turned off. For this situation, the diode of transistor $Q_3$ is utilized for freewheeling. The switches in the front-end converter stay in their past states.

(a) Mode 1: Output voltage = ±$V_{IN1}$ state (b) Mode 2: Output voltage = ±$V_{IN0}$ state.

(c) Mode 3: Output voltage = ±($V_{IN0}+V_{IN1}$) state (d) Mode 4: Output voltage = 0 V state.

At Output voltage = ±$V_{IN1}$, the net voltage that shows up over the DC transport currently is equivalent to $V_{IN0}+V_{IN1}$.

The output voltage is communicated as:

At right now charging vitality is given as:

The normal output voltage of buck help converter can be communicated utilizing Eq. (5):

The vitality discharged by the circuit at switch s1a by the proposed converter given by Eq. (6):

The proposed converter BB with lessening exchanging misfortunes are communicated in condition Eq. (7):

Voltage variety over the capacitor C1 can be communicated by Eq. (8):

Operation modes 3 and 4: Capacitor $C_1$ charged to $V_{IN1}$, is connected in series with input voltage source $V_{IN0}$ by turning ON transistors $S_{1a}$ and $S_{1b}$. Diode $D_{1b}$ is reverse biased and blocks $V_{IN1}$. To obtain zero level at the output after the positive half cycle only transistor $Q_1$ is turned ON, while all the other switches in the H-bridge inverter remain turned OFF. The diode of transistor $Q_2$ is employed for free-wheeling. Similarly, to obtain zero level at the output after the negative half cycle, only transistor $Q_4$ is turned ON, while all the other switches in the full extension inverter stay turned off. The net voltage that shows up over the DC transport currently is equivalent to $V_{IN0}+V_{IN1}$. are appeared in Fig. 5(c) and 5(d).

Capacitor $C_1$ charged to $V_{IN1}$, is associated in arrangement with info voltage source $V_{IN0}$ by turning ON transistors $S_{1a}$ and $S_{1b}$ the present changes from $I_3$ to $I_4$. The voltage over the inverter circuit is communicated as:

The vitality discharged by the circuit at switch $s_{1a}$ by the proposed converter given by Eq. (10):

The normal output voltage of buck help converter II is acquired utilizing Eq. (11):

The proposed converter BB with lessening exchanging misfortunes are communicated in condition Eq. (12):

A model of single-stage BBDCLCMLIFIM-based engine is structured and executed for 230 V ($V_{max}$) output voltage. The examples of PWM pulses, Simulink display and the output voltage utilizing n-levels are appeared in Figs. 6(a) and (b).

Fig. 6a) PWM pulses, b) topology of a flying capacitor multilevel inverter

a)

b)

Rectifier units, buck boost converter units, controller units, driver units, DC-connection and H-bridge inverter units are incorporated in this model. The rectifier units are planned utilizing a scaffold rectifier (MICBR1010) and a capacitive channel of 1000 μF. The outputs of rectifier units go about as the contribution for the lift chopper units and battery banks. The buck support converter are manufactured utilizing IRF840 controlled power gadgets (MOSFET) switches and aloof segments ($C_1=C_2=$ 100 μF). The dspic gives control signs to the MOSFET driver circuit. The highlights of dspic are utilized to accomplish effective control of the proposed framework. The DCLM and H-bridge inverter frameworks are manufactured utilizing IRF840 control MOSFET switches. The experiment identical circuit of BBDCLCMLIFIM framework is appeared in Fig. 22. Output voltage across capacitor $C_2$ can be expressed by (13):

2.2.2. Buck boost converter conduction losses

With reference MOSFET switching losses are determined utilizing the exact voltage drop with arrangement straight resistor ($RD=$ 0.07). It decides the terminal entryway by terminal source voltage and intersection temperature. The misfortunes in the MOSFET switch are given in Eq. (19).

$P\left(cond{S}_2\right)=I_{S_{\mathrm{1,2}}}^2\times RDS$ on:

19

$I{\left(S_{\mathrm{1,2}}\right)}^2=D_2\times \left[I{\left(O{S}_{\mathrm{1,2}}\right)}^2+\frac{∆I{\left(O{S}_{\mathrm{1,2}}\right)}^2}{12}\right],$

where ($I{s}_{\mathrm{1,2}}$) shows the present coursing through the switch ($S_1$), ($S_2$) represents the “ON” time of switch and delta $I_2$ represents the normal swell current of switch. Exchanging ampere decided as ($I\left(O_{S2}\right)$) is gotten from Eq. (20). Initial current $∆I_{S_{\mathrm{1,2}}}$ are given as in Eq. (20):

20

$∆I\left(OS\mathrm{1,2}\right)=\frac{I\left(O{S}_{\mathrm{1,2}}-max\right)-\left(IO{S}_{\mathrm{1,2}}-min\right)}{2}=\frac{8.53-6.6}{2}=0.965,$

where ($I(S_{\mathrm{1,2}}-max)$) and ($I(S_{\mathrm{1,2}}-min)$) gives high and low sizes of intensity controlled gadget current ($S_1$-$S_8$) as outlined in Fig. 7. From Fig. 8, $D2=$ 0.22, $I_{S_2}=$ 7.565 and $∆I_{O{S}_{\mathrm{1,2}}}=$ 0.965, which are substituted in Eq. (21), total ripples and losses are gotten from MOSFET switches [18] as settled and conduction losses are determined in Eq. (21), (22):

21

$I{\left(S_{\mathrm{1,2}}\right)}^2=12.58\mathrm{A},$

22

$P\left(\mathrm{c}\mathrm{o}\mathrm{n}d{S}_{\mathrm{1,2}}\right)=12.58\times 0.069=0.90\mathrm{W}.$

Power devices conveyance losses ($S_{\mathrm{1,2}}$) during starting.

Fig. 7Conduction of power devices at open loop condition [18]

3.1. Simulation performance evaluation

The designed control topology is striving with a perfect three-stage connection with a two-phase BBC power supply and an induction motor. Table 2 shows the simulation specifications, which supports in reducing the harmonic distortion.

3.2. Output voltage before H-bridge inverter for single pulse

The output voltage before H-bridge inverter for single PWM pulse is shown in Fig. 9. It produces a maximum voltage of sum of $V_{1N1}$ and $V_{1N0}$.

3.3. Output voltage and current for single PWM pulse

The output voltage and current of multilevel inverter for single pulse input is shown in Fig. 10 and Fig. 11.

Fig. 8Converter: a) diode conduction losses b) ripple currents across inductor, diodes and capacitor [17]

a)

b)

The output waveform with seven steps produces a staircase wave which reduces the harmonic distortion. Single pulse multilevel inverter is an existing system. To improve the performance the single pulse is replaced by sine pulse. Our proposed system has sine signal compared with ramp signal as an input pulse. It reduces harmonic distortion than single pulse. The simulation outputs for sine pulse are given below. The multilevel inverter switches receives the converter outputs. The recreation parameters of the designed model are set as follows: input voltage = 480 V, input current = 27 A, input supply frequency = 50 Hz, exchanging frequency = 2 kHz, resistance =20 Ω and inductance = 310 mH for 7 level inverter. The output voltages are synthesized using the MATLAB platform. Multilevel inverters with 7-levels output voltage synthesis are shown in Fig. 13, 14 and 15.

Fig. 9Output voltage before H-bridge inverter

Fig. 10Output voltages after H-bridge inverter

Fig. 11Output current after H-bridge inverter

3.4. Voltage across capacitor for sine pulse

Capacitor gets charged and maintains it ideally and then it gets discharged. The voltage across the capacitor for sine pulse modulation is shown in Fig. 12.

3.5. Output voltage before H-Bridge inverter

The output voltage before H-bridge inverter for sine PWM pulse is shown in Fig. 13. It produces a maximum voltage of sum of $V_{1N1}$ and $V_{1N0}$.

Fig. 12Voltage across capacitor for sine PWM

Fig. 13Output voltage before H-bridge inverter

3.6. Output voltage and current for sine PWM pulse

The output voltage and current of multilevel inverter for sine pulse input is shown in Fig. 14 and Fig. 15.

The output waveform with seven steps produces a staircase wave which reduces the harmonic distortion.

Fig. 14Output voltage after H-bridge inverter

3.7. THD analysis

The THD % for single pulse and sine pulse at modulation index 1 are shown in Fig. 16.

THD for various modulation indices.

The comparisons of THD percentage of single pulse and sine pulse for different modulation indices are tabulated in Table 3.

Fig. 15Output current after H-bridge inverter

Fig. 16a) THD results for single pulse, b) THD results for sine pulse

a) Fundamental (50 Hz) = 367.9 THD = 17.08 %

b) Frequency (50 Hz) = 282.1 THD = 8.11 %

3.8. Analysis of speed regulation in pumping process of RO section in textile wastewater treatment

The block diagram of speed control system is shown in the Fig. 17.

The pumping process parameters, pressure and flow are optimized by adjusting the electrical parameters, duty cycle and speed. The proposed Fuzzy Logic Control (FLC) system has two inputs: the first input is the difference in actual and desired flow; the second input is the difference in actual and desired pressure. FLC is applied to the speed controlling system to control the speed of the induction motor. The output of FLC is sent to the three-phase inverter to produce waveform with variable frequency to control the speed of the three phase induction motor. For fuzzy logic controller, ranges for membership functions have to be defined. The range of input variables pressure (PR), flow (FL) and output variable duty cycle are defined as Negative Large (NL), Negative Medium (NM), Negative Small (NS), Zero (ZE), Positive Small (PS), Positive Medium (PM), Positive Large (PL). The output variable is used to calculate the needed change of frequency which will be used to control the speed of induction motor. All fuzzy rules used in the proposed system are summarized in the Table 4.

Fig. 18 shows the fuzzy membership function of fuzzy controller for speed controlling system with inputs and output of the system.

Table 5 shows the variation of electrical parameter values with respect to process parameters.

Fig. 17Block diagram of speed control system

Whenever there is a deviation of process parameter value from set point, fuzzy controller takes immediate control action by sensing the change of values. By changing the duty cycle, frequency of the supply that is fed to the inverter is varied. Consequently, the rotor speed can be varied. Instead of running the motor at full frequency of 50 Hz during the entire day, the frequency can be reduced when the load reduces, and energy consumption can be reduced. Fig. 19 shows the rotational speed of rotor in rpm. The speed of the motor obtained for the corresponding pressure and flow is 900 rpm.

Fig. 20 and Fig. 21 shows the discharge flow rate and discharge pressure of the pumping process. The obtained flow and pressure values are 188 gpm and 15.98 psi for 900 rpm.

Fig. 18Membership function for speed controller

Fig. 19Rotor speed of the motor

Fig. 20Discharge flow rate of the pump

Fig. 21Discharge pressure of the pump

Whenever there is a deviation of process parameter value from set point, fuzzy controller takes immediate control action by sensing the change of values. By changing the duty cycle, frequency of the supply that is fed to the inverter is varied. Consequently, the rotor speed can be varied. Instead of running the motor at full frequency of 50 Hz during all the day, the frequency can be reduced when the load reduces, and energy consumption can be reduced.

3.9. Experimental evaluation

The converter outputs are encouraged to staggered inverter switches for the application for the material water siphoning process with the fluffy rationale controller. The experimental parameters are set as pursues: supply recurrence = 50 Hz, input voltage = 480 V, input current = 27 A, trading recurrence = 2 kHz, opposition = 20 Ω, inductance = 310 mH. Table 6 demonstrates engine parameters. The acknowledgment equipment circuits are appeared in Fig. 22. Block diagram and Prototype Model equipment of BBDCLCMLIFIM appeared in Fig. 23 and 24. The structured BBDCLCMLIFIM analysis were carried out and hence the proposed method achieves reduced THD which is more cost effective and efficient for the various industry applications.

Fig. 22Realization of hardware circuit diagram of BBDCLCMLIFIM

Fig. 23Experimental block diagram of BBDCLCMLIFIM

Fig. 24Prototype hardware of BBDCLCMLIFIM with vibration sensor for pumping applications in textile wastewater treatment